Chapter 4: Processor Architecture

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Processor Architecture

Aside The progress of computer technology

4.1 The Y86-64 Instruction Set Architecture

4.1.1 Programmer-Visible State

4.1.2 Y86-64 Instructions

4.1.3 Instruction Encoding

Aside Comparing x86-64 to Y86-64 instruction encodings

Practice Problem 4.1 (solution page 516)

Practice Problem 4.2 (solution page 517)

Aside RISC and CISC instruction sets

Aside The RISC versus CISC controversy

4.1.4 Y86-64 Exceptions

4.1.5 Y86-64 Programs

Practice Problem 4.3 (solution page 518)

Practice Problem 4.4 (solution page 518)

Practice Problem 4.5 (solution page 519)

Practice Problem 4.6 (solution page 519)

4.1.6 Some Y86-64 Instruction Details

Practice Problem 4.7 (solution page 520)

Practice Problem 4.8 (solution page 520)

Aside Getting the details right: Inconsistencies across x86 models

4.2 Logic Design and the Hardware Control Language HCL

Aside Modern logic design

4.2.1 Logic Gates

4.2.2 Combinational Circuits and HCL Boolean Expressions

Practice Problem 4.9 (solution page 520)

4.2.3 Word-Level Combinational Circuits and HCL Integer Expressions

Practice Problem 4.10 (solution page 520)

Practice Problem 4.11 (solution page 520)

Practice Problem 4.12 (solution page 520)

4.2.4 Set Membership

4.2.5 Memory and Clocking

Aside Real-life memory design

4.3 Sequential Y86-64 Implementations

4.3.1 Organizing Processing into Stages

Practice Problem 4.13 (solution page 521)

Aside Tracing the execution of a subq instruction

Aside Tracing the execution of an rmmovq instruction

Practice Problem 4.14 (solution page 522)

Practice Problem 4.15 (solution page 522)

Aside Tracing the execution of a pushq instruction

Practice Problem 4.16 (solution page 522)

Practice Problem 4.17 (solution page 522)

Aside Tracing the execution of a je instruction

Practice Problem 4.18 (solution page 523)

Aside Tracing the execution of a ret instruction

4.3.2 SEQ Hardware Structure

4.3.3 SEQ Timing

PRINCIPLE: No reading back

4.3.4 SEQ Stage Implementations

Fetch Stage

Practice Problem 4.19 (solution page 523)

Decode and Write-Back Stages

Practice Problem 4.20 (solution page 524)

Practice Problem 4.21 (solution page 524)

Practice Problem 4.22 (solution page 524)

Execute Stage

Practice Problem 4.23 (solution page 524)

Practice Problem 4.24 (solution page 524)

Memory Stage

Practice Problem 4.25 (solution page 524)

Practice Problem 4.26 (solution page 525)

Practice Problem 4.27 (solution page 525)

PC Update Stage

Surveying SEQ

4.4 General Principles of Pipelining

4.4.1 Computational Pipelines

4.4.2 A Detailed Look at Pipeline Operation

4.4.3 Limitations of Pipelining

Nonuniform Partitioning

Practice Problem 4.28 (solution page 525)

Diminishing Returns of Deep Pipelining

Practice Problem 4.29 (solution page 526)

4.4.4 Pipelining a System with Feedback

4.5 Pipelined Y86-64 Implementations

4.5.1 SEQ+: Rearranging the Computation Stages

Aside Where is the PC in SEQ+?

4.5.2 Inserting Pipeline Registers

4.5.3 Rearranging and Relabeling Signals

Aside What is the difference between signals M_stat and m_stat?

4.5.4 Next PC Prediction

Aside Other branch prediction strategies

Aside Return address prediction with a stack

4.5.5 Pipeline Hazards

prog2

# prog3

# prog4

Avoiding Data Hazards by Stalling

Aside Enumerating classes of data hazards

Avoiding Data Hazards by Forwarding

# prog2

prog3

# prog4

Load/Use Data Hazards

Avoiding Control Hazards

4.5.6 Exception Handling

4.5.7 PIPE Stage Implementations

PC Selection and Fetch Stage

Practice Problem 4.30 (solution page 526)

Decode and Write-Back Stages

Practice Problem 4.31 (solution page 526)

prog8

Practice Problem 4.32 (solution page 526)

Practice Problem 4.33 (solution page 527)

Practice Problem 4.34 (solution page 527)

Execute Stage

Practice Problem 4.35 (solution page 527)

Memory Stage

4.5.8 Pipeline Control Logic

Desired Handling of Special Control Cases

prog6

Detecting Special Control Conditions

Pipeline Control Mechanisms

Combinations of Control Conditions

Practice Problem 4.37 (solution page 528)

Practice Problem 4.38 (solution page 528)

Control Logic Implementation

Practice Problem 4.39 (solution page 529)

Practice Problem 4.40 (solution page 529)

Practice Problem 4.41 (solution page 529)

Practice Problem 4.42 (solution page 529)

4.5.9 Performance Analysis

Aside Testing the design

Aside Formally verifying our design

Web Aside ARCH:VLOG Verilog implementation of a pipelined Y86-64 processor

Practice Problem 4.43 (solution page 530)

Practice Problem 4.44 (solution page 530)

4.5.10 Unfinished Business

Multicycle Instructions

Interfacing with the Memory System

4.6 Summary

Aside State-of-the-art microprocessor design

Web Aside ARCH:HCL HCL descriptions of Y86-64 processors

4.6.1 Y86-64 Simulators

Bibliographic Notes

Homework Problems

4.45 ◆

4.46 ◆

4.47 ◆◆◆

4.48 ◆◆

4.49 ◆◆◆

4.50 ◆◆◆

4.51 ◆

4.52 ◆◆

4.53 ◆◆◆

4.54 ◆◆

4.55 ◆◆◆

4.56 ◆◆◆

4.57 ◆◆◆

4.59 ◆◆

Solutions to Practice Problems

Solution to Problem 4.1 (page 396)

Solution to Problem 4.2 (page 396)

Solution to Problem 4.3 (page 405)

Solution to Problem 4.4 (page 406)

Solution to Problem 4.5 (page 406)

Solution to Problem 4.6 (page 406)

Solution to Problem 4.7 (page 406)

Solution to Problem 4.8 (page 407)

Solution to Problem 4.9 (page 410)

Solution to Problem 4.10 (page 413)

Solution to Problem 4.11 (page 415)

Solution to Problem 4.12 (page 416)

Solution to Problem 4.13 (page 423)

Solution to Problem 4.14 (page 426)

Solution to Problem 4.15 (page 427)

Solution to Problem 4.16 (page 428)

Solution to Problem 4.17 (page 429)

Solution to Problem 4.18 (page 430)

Solution to Problem 4.19 (page 442)

Solution to Problem 4.20 (page 443)

Solution to Problem 4.21 (page 444)

Solution to Problem 4.22 (page 444)

Solution to Problem 4.23 (page 445)

Solution to Problem 4.24 (page 445)

Solution to Problem 4.25 (page 446)

Solution to Problem 4.26 (page 446)

Solution to Problem 4.27 (page 447)

Solution to Problem 4.28 (page 453)

Solution to Problem 4.29 (page 454)

Solution to Problem 4.30 (page 485)

Solution to Problem 4.31 (page 485)

Solution to Problem 4.32 (page 488)

Solution to Problem 4.33 (page 488)

Solution to Problem 4.34 (page 489)

Solution to Problem 4.35 (page 490)

Solution to Problem 4.36 (page 491)

Solution to Problem 4.37 (page 497)

Solution to Problem 4.38 (page 498)

Solution to Problem 4.39 (page 499)

Solution to Problem 4.40 (page 500)

Solution to Problem 4.41 (page 500)

Solution to Problem 4.42 (page 500)

Solution to Problem 4.43 (page 504)

Solution to Problem 4.44 (page 504)