fa26-cs759 cs759
Lecture 04: Instruction-Level and Thread-Level Parallelism Lecture 04: Instruction-Level and Thread-Level Parallelism
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Code of the day: comparing sign bits
Registers and instruction execution
Register roles
Why register capacity is limited
Pipelining: overlap the stages of different instructions
Instruction stages versus clock cycles
Three-store timing example
Latency, throughput, and balance
Pipeline hazards
Multiple issue and other ILP strategies
Thread-level parallelism
Processes and threads
Why add threads?
Hyper-Threading and simultaneous multithreading
Three hardware multithreading policies
Putting ILP and TLP together