Lecture 17: CUDA Kernel Scheduling and Thread Divergence

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Opening quiz: right shifts and signedness

Two levels of scheduling

Blocks are divided into warps

Quiz: resident warp count

Readiness and latency hiding

Choose blocks that provide useful warps

Divergence within a warp

Quiz: a race hidden inside divergent code

Branchless expressions have assumptions

Volta and independent thread scheduling

Memory hierarchy and register pressure