The Microarchitecture of the LC-3

Content locked

The catalog is public. Reading this content requires approved access.

C.1 Overview

C.2 The State Machine

C.3 The Data Path

C.4 The Control Structure

C.5 The TRAP Instruction

C.6 Memory-Mapped I/O

C.7 Interrupt and Exception Control

C.7.1 Initiating an Interrupt

C.7.2 Returning from an Interrupt or Trap Service Routine, RTI

C.7.3 Initiating an Exception

C.7.3.1 Privilege Mode Exception

C.7.3.2 Illegal Opcode Exception

C.7.3.3 Access Control Violation (ACV) Exception

C.8 Control Store

Source