Chapter 3: Digital Logic Structures

Chapter 3: Digital Logic Structures

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Digital Logic Structures

3.1 The Transistor

3.2 Logic Gates

3.2.1 The NOT Gate (Inverter)

3.2.2 OR and NOR Gates

3.2.3 Why We Can’t Simply Connect P-Type to Ground

3.2.4 AND and NAND Gates

3.2.5 Gates with More Than Two Inputs

3.3 Combinational Logic Circuits

3.3.1 Decoder

3.3.2 Mux

3.3.3 A One-Bit Adder (a.k.a. a Full Adder)

3.3.4 The Programmable Logic Array (PLA)

3.3.5 Logical Completeness

3.4 Basic Storage Elements

3.4.1 The R-S Latch

3.4.2 The Gated D Latch

3.5 The Concept of Memory

3.5.1 Address Space

3.5.2 Addressability

3.5.3 A 22-by-3-Bit Memory

3.6 Sequential Logic Circuits

3.6.1 A Simple Example: The Combination Lock

3.6.2 The Concept of State

3.6.3 The Finite State Machine and Its State Diagram

3.6.4 The Synchronous Finite State Machine

3.6.5 The Clock

3.6.6 Example: A Danger Sign

3.7 Preview of Coming Attractions: The Data Path of the LC-3

Exercises

3.13 The following logic diagram produces the logical value OUT.

3.14 The following logic circuits consist of two exclusive-OR gates. Construc the output truth table.

3.15 Fill in the truth table for the logical expression NOT(NOT(A) OR NOT(B)). What single logic gate has the same truth table?

3.33 For this question, refer to the figure that follows.

★3.58

3.59

★3.61 The logic diagram shown below is a finite state machine.

★3.62

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